This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-295191, filed Oct. 8, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to an embedded memory which causes a fuse box outside a memory macro to transfer address information for redundancy to the memory macro.
2. Description of the Related Art
In the field of ASIC (Application Specific Integrated Circuit), more and more embedded memories with large capacity have been used in recent years. With the increasing use of such memories, multimedia applications and SoC (System on Chip) have been realized.
In memory macros, such as DRAMs (Dynamic Random Access Memories) or SRAMs (Static RAMs), it is essential to provide a redundant circuit for relieving defective cells to produce acceptable products. The redundant circuit is such that, when a defect has been found in an ordinary cell, the defective cell is replaced with a spare memory cell, thereby relieving the defective cell. Generally, defective cells are replaced in units of a set of spare memory cells. That is, defective cells are relieved in rows, columns, or blocks.
To replace a defective cell with a spare, it is necessary to store an address (or a faulty address) specifying the defective cell. Such a faulty address is generally stored in an element called a fuse.
There are several types of fuses. In memory macros, such as DRAMs or SRAMs, optical fuses are generally used. An optical fuse is such that an interconnection line in a specific layer is fused by heat generated as a result of the projection of laser light. In the case of an optical fuse, one bit of data is stored, depending on whether the interconnection line is cut. Such optical fuses are mainly used in relieving the defective cells found in a test carried out before the chip is sealed into a package.
The element size (interconnection line width) of the optical fuse is determined by the wavelength of the laser light used. This prevents the element size from keeping pace with the miniaturization of the circuits in a chip. Consequently, the optical fuse is larger in size than a semiconductor element, such as a transistor. Furthermore, the optical fuse is such that laser light is projected directly onto the fuse to fuse it. Therefore, another interconnection line or connection electrode cannot be formed on the optical fuse. Generally, no circuit is provided under the optical fuse to prevent damage to the circuit due to physical destruction known as fusing.
For the above reasons, arranging optical fuses in a memory micro results in the occupation of a large area. In addition, the arrangement places strict restrictions on the floor plan or interconnection layout. A Flip Chip BGA (flip chip ball grid array) has a structure where the chip is connected directly to a wiring board via connection electrodes called bumps formed on the chip. As a result, when this package is selected, the following problem arises: bumps cannot be formed on the optical fuses.
To solve the above problem, the following method has been considered: optical fuses are provided together outside a memory macro and the fuse data stored in the individual optical fuses is transferred to the memory macro at the time of the initialization of the memory macro.
Hereinafter, a device into which optical fuses and a circuit necessary to read and transfer the fuse data are placed together is referred to as a fuse box. The fuse box may be shared by a plurality of memory macros. In such a case, a very large number of optical fuses are included in the fuse box.
At the level of actual products, most of the spare memory cells are left unused. In that case, the optical fuses corresponding to the unused spare memory cells are also left unused. As a result, when the data stored in all of the optical fuses is regarded as a bit string, an unprogrammed state xe2x80x9c0 (the fuse is uncut)xe2x80x9d appears consecutively more frequently than a programmed state xe2x80x9c1 (the fuse is cut)xe2x80x9d. In the case of such biased data, data compression is very effective. Therefore, compressed data is programmed in the optical fuses. Then, the data is expanded at the time of data transfer. This enables the area of the fuse box to be reduced remarkably, even if a logic circuit for data expansion is added. A fuse box with such a logic circuit that expands the compressed programmed fuse data has been already proposed (for example,
xe2x80x9cShared fuse macro for multiple embedded memory devices with redundancyxe2x80x9d, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, pp. 191-194, 2001).
When the term fuse is simply used, it usually means an optical fuse. There is another type of fuse known as an electrical fuse. An electrical fuse stores data by changing the state of an element electrically. Electrical fuses are divided into various types according to the elements used as fuses and the method of storing data. They includes a fuse that fuses the interconnection line by Joule heat generated by causing a large current to flow through the line and a fuse that destroys the insulating film of the element by applying a high voltage. An electrical fuse of the type that destroys the insulating film of the element is in the insulated state before data is written into the fuse and in the conducting state after data is written into the fuse. Therefore, this type of fuse is sometimes called anti-fuse.
Electrical fuses are chiefly used to relieve defective cells found in a test carried out after the chip is sealed into a package. They can also be used to tune the circuits. Therefore, use of electrical fuses is expected to improve the yield and therefore electrical fuses are requested to be mounted on the chips.
Use of electrical fuses doesn""t necessarily mean that optical fuses are not required. For example, in the stage of wafers, optical fuses are used to relieve a large number of defective cells. A small number of defective cells occurred after the packaging are relieved by use of electrical fuses.
In a case where electrical fuses are mounted on a chip, when an attempt is made to distribute the electrical fuses in the inside of each memory macro in an ASIC, even if the fuses are to be used for a small number of defective cells, the following problem arises. When a large current or a high voltage is externally supplied, the number of connection terminals used is limited. Therefore, the power supply lines have to be connected in common to each memory macro. The power supply lines must be made very strong so as not to cause a voltage drop. There is a method of providing an internal high voltage generator near each memory macro. The high voltage generator, however, occupies a large circuit area. It is very undesirable to have a plurality of high voltage generators in a chip, although they are not used at all in an actual memory operation. Therefore, putting the electrical fuses together in a fuse box is effective.
The faulty addresses programmed in a plurality of fuses put together in a fuse box, or the so-called fuse data, are transferred from the fuse box to a memory macro at the time of initialization. When only optical fuses are present in the fuse box, the contents are simply transferred serially to the memory macro.
As shown in FIG. 15, when in a semiconductor integrated circuit device (or embedded memory), a single fuse box 101 is shared by a plurality of memory macros (DRAM Macro) 201, (DRAM macro) 202, and (SRAM Macro) 203, the individual memory macros 201, 202, 203 are connected in a daisy chain. This enables the fuse data to be sent through simple serial transfer.
However, when both optical fuses and electrical fuses are provided in the fuse box, it is necessary to know not only faulty addresses but also the time when the data in the electrical fuses is to be transferred. In that case, it is important to deal with all combinations corresponding to the types and configurations of memory macros, such as what number spare in what number DRAM macro, what number spare in another DRAM macro, and what number spare in what number SRAM macro. The number of such combinations is enormous. To change the hardware configuration of the fuse box according to all of the combinations requires the design and verification works each time a change is made, which is not desirable.
Concerning the transfer of fuse data, there is a method of separating an optical fuse data path from an electrical fuse data path. There is another method of replacing the data in the optical fuses with the data in the electrical fuses in a certain set of fuses. In those methods, however, the circuits for the fuse data paths in the memory macros are complicated. To prevent the circuits from being complicated, the number of fuse sets corresponding to the electrical fuses must be limited or spare memory cells only for electrical fuses have to be prepared additionally.
According to an aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a memory cell array in which a plurality of memory cells are arranged in an array, a redundant circuit which has a plurality of spare memory cells and replaces defective memory cells in the memory cell array with specific spare memory cells on the basis of programmed address information, a memory circuit with a plurality of nonvolatile memory elements in which the address information is programmed, a transfer circuit which transfers the address information programmed in the memory circuit to the redundant circuit and the operation of which is controlled according to command information programmed in the memory circuit.